Equivalent to std::atomic_thread_fence, except no CPU instructions for memory ordering are issued.
Only reordering of the instructions by the compiler is suppressed as order instructs.
Before C++11, usually this is coded with same affect:
// Equivalent to a full compiler-only memory barrier (like memory_order_seq_cst)
__asm__ __volatile__("" ::: "memory");
or on M$ platform:
// Equivalent to a compiler-only memory barrier
_ReadWriteBarrier();
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