Resource:
https://en.wikipedia.org/wiki/Intel_5-level_paging
The adoption of 5-level paging (also known as LA57) allows the virtual address space to expand from the traditional 48 bits (256 TiB) to 57 bits (128 PiB).
In 5-level paging (LA57), the "free" or unused bits are indeed bits 57 through 63, which totals 7 bits. However, there is a catch: those bits aren't truly "free" for software to store random data (like tags or metadata) unless a specific hardware feature like Intel LAM (Linear Address Masking) or AMD UAI (Upper Address Ignore) is enabled.
The Breakdown of the 64-bit Address
Here is how the 64 bits are partitioned in a 5-level paging system:- Bits 0–11: Page Offset (4 KB boundaries).
- Bits 12–56: The actual translation bits used by the five levels of page tables 9 x 5 = 45 bits
- Bits 57–63: The 7 unused bits.
The "Canonical" Constraint
The CPU enforces a rule called Canonical Form. For an address to be valid:Bits 57 through 63 must be an exact copy of bit 56.
If bit 56 is 0, then bits 57–63 must all be 0.
If bit 56 is 1, then bits 57–63 must all be 1.
If software tries to use an address where those 7 bits are "dirty" (containing random data), the CPU will trigger a General Protection Fault (#GP). This is why programmers can't simply use those 7 bits for pointers without the masking features mentioned above.
